Example embodiments of the inventive concepts relate to a decoder using a low-density parity-check (LDPC) code and/or a memory controller including the same.
In the field of semiconductor memory, errors occurring due to noise may be corrected using coding and decoding technology based on error correction codes. Among these error correction codes, the LDPC code which uses an iterative operation based on a probability has received attention.
A strong error may occur in a NAND flash memory device, where the strong error is an error which makes a large value allocated to an absolute value of a channel log-likelihood ratio (LLR) of a decoder because of its high degree of interference among errors occurring due to interference between the program states of adjacent cells. The strong error may significantly deteriorate the error correction performance of the decoder using the LDPC code. In a NAND flash memory device having a high strong error ratio, the correction performance of an LDPC decoder may greatly decrease.